Student Symposium 2015

Spring 2015
Project Title & Student Name

Atmospheric Water Generator Retrofit
Edward Trinh, Emil Kurian, Michael Fung, BSEE  
The purpose of this proposal is discussing low power DSP design for undergraduate students’ senior project. The low power DSP integrated circuit can be used in field of the medical devices. Specifically, the hearing aid devices require low power DSP integrated circuit. There are different types of filters, we chose FIR filter to design low power DSP integrated circuit. The FIR filter contents three main parts: delay, multiplication, and adder. We chose Ripple Carry Adder because it has low power dissipation. This proposal also discusses marketing research, theory of filters, uniqueness of project, resources, schedule, work assignments, and preliminary work. We design the low power DSP integrated circuit, and we learn how to researching information, making engineering decision, using resources, working in group, solving problems, and getting best results.
Son Nguyen, Chris Sawtelle, Gene Sirovskiy, Jennifer Uvira, BSEE  
Our proposed idea is to develop electric car charging stations that do not rely on the grid during peak hours. Through our research, we have discovered that the power grid has an unsolved problem with utilization timing. The electric grid is utilized far too much during certain hours of the day which requires backup coal systems to be turned on in order to meet the demand. These coal systems are difficult to manage as they take time to ramp up when turned on and to cool down after operation.
Low Power DSP
Gerardo Narvaez, Ryan Lin, Wei Li, BSEE  
The purpose of this proposal is discussing low power DSP design for undergraduate students’ senior project. The low power DSP integrated circuit can be used in field of the medical devices. Specifically, the hearing aid devices require low power DSP integrated circuit. There are different types of filters, we chose FIR filter to design low power DSP integrated circuit. The FIR filter contents three main parts: delay, multiplication, and adder. We chose Ripple Carry Adder because it has low power dissipation. This proposal also discusses marketing research, theory of filters, uniqueness of project, resources, schedule, work assignments, and preliminary work. We design the low power DSP integrated circuit, and we learn how to researching information, making engineering decision, using resources, working in group, solving problems, and getting best results.
USB interface multi-channel multimeter/oscilloscope with schematic simulator real-time integration
Evan Kashi, Gytis Baranauskas, BSEE  
The goal of our project is to create a cost effective measurement device that has the capability to be used in conjunction with circuit simulator software (such as LTSpice). The product will have the convenient capability of being USB compatible and powered, resulting in a direct connection to software, and being able to test the circuit. Currently we are working on integrating the device with open-source software (Quite Universal Circuit Simulator aka QUCS). At this time, specifically, we are trying to generate waveforms in real-time on the simulator using streaming data. We also want to implement a scalable range, so that we can measure both large and small characteristics with high accuracy. After verifying the functionality of our device and testing it thoroughly, we would hope to then present the open-source results to an established company, like Linear Technology, who can enable us to further the potential of this idea.
Bio-medical Database
Anudeep Kasturi, Janice Pham, Jose Zopiyatle, Truong Dang, BSEE  
This project is a Biomedical Database product called SEAL that will contain patient information and have the ability to be accessed by personal ID information. SEAL stands for security in internal database, efficiency check in time for patients, affordable hospitals upgrade to electronic database, and limitless amount of opportunities in the health care industries. Currently, the market has competitors only making either electronic medical systems or personal verification devices for hospitals, but our product will combine both of these features. SEAL will include features such as sign-in capabilities through an assigned RFID card for each patient, fingerprint data, a PIN number, and a database of patient information that can be accessed by hospital personnel.
18 Channel Scope-dongle
Jacqueline Chee, Noe Quintero, Fredrick Sun, BSEE  
The project that our group will be creating is an 18 channel oscilloscope. The system will be composed of an amplifier circuit, FPGA, ADCs, a USB Interface Chip, and software for displaying the waveforms. The system behavior will follow a pipeline of several stages. As an input voltage signal travels in, a board responsible for signal conditioning will alter the signal so it is of appropriate voltage for the next stage. After the input signal is “conditioned,” it will go through the ADC to be converted into digital values. The ADC to be used is the LTC2351. This particular ADC has 6 channels for sampling and holding the signal. Our oscilloscope will have 18 channels, thus three LTC2351 chips will be used. The ADC will be managed by the FPGA. The FPGA will be responsible for reading the values from the three ADCs. The data from the ADC will be packed in such a way that it can be exported to the FTDI chip. The FTDI chip will serialize the data so that it can be imported into the PC. A C# program will then analyze the data that is imported in and display the correct waveforms on the screen. There will be various oscilloscope options on the GUI such that the functionality is similar to a physical oscilloscope. The components needed will be provided by Linear Technology.
Baby Car Seat Sensor
Elizabeth Lee, Michelle Chin, Eshetie Liku, BSEE  
Concern for the safety of children stuck in hot cars has been brought to our attention after learning about how many children die after having been left in either hot or cold cars. Although many children are saved from death, they suffer from either hyperthermia or hypothermia because they are left in the car too long. This has spurred our team to come up with a baby car seat sensor that can prevent children from being left in hot cars. Using the Arduino Uno board, sensors, such as temperature, weight, and seat belt, are used to determine whether there is a child in the car seat before going through the procedures to inform the parents. When there is a child left in the car, the sensors will set off an alarm that will inform the parents that they left their child in the car as well as inform people around the car that there is a child stuck in a hot car and is in need of help. In hopes that the baby car seat sensor can be accessible to as many families as possible, we want to create a product that is low-cost but still user friendly. With our baby car seat sensor, we want to prevent any more cases of children being left unattended in cars.
Three Channel SMPS
Robert Richardson, Neil Rodas, BSEE  
Currently there is a need for a device which can replace rectifier vacuum tubes in guitar amplifiers, vintage radios, and other tube applications. We have developed a project proposal for a Switch Mode Power Supply (SMPS) that replaces the old vacuum tube and power supply. The SMPS has a Flyback circuit and a two switch Forward circuit to step up and step down DC voltages needed for amplifier tube operation. The team has identified the resources and effort needed to complete the project. This paper outlines the preliminary work completed and the future actions needed to make a tube replacement switch mode power supply.
Autonomous Sanitizing Robot
Darren Ng, Robert San, Lawrence Blanco, Eric Zhong, BSEE  
Ultraviolet (UV) light is part of the invisible spectrum that can be used for germicidal purposes due its high energy. Based on an analysis of existing automated cleaning products in the United States, the products did not utilize UV for cleaning or were not easily moveable. A small, mobile robot, with mounted germicidal UVC lights could fill the gap left by other products. To create the robot, an Arduino microcontroller will be used to control navigation, handle user input, and manage the UV lights. Taking consideration of the parts used in the robot, a budget of 180 dollars has been allocated towards the project. Under this budget and a defined schedule, a working prototype is estimated to be created by May 2015.
Helmet Heads-up Display
Adrian Aguayo, Jorge Balderrama, Jonathan Garay, Arvin Jami, James Muller, BSEE  
Our group will endeavor to realize a motorcycle heads up display that will include the features in (rev. 1.0) listed in the roadmap of concept below. In order to focus on the most important aspects of our idea, all the features cited in rev 2.0 will be tentative development and could be subjected to follow up by future senior groups.
UAV Cloud Seeding
Tenyie Peng, Chun Weng, Kevin Yu, Musfir Subzwari, BSEE  
Current methods of cloud seeding to combat the drought in California include releasing seeding agents such as silver iodide or dry ice into the air with a ground generator or dispensing them with a piloted aircraft flying over the clouds. The project outlined in this proposal will aim to create an unmanned aerial vehicle (UAV) model, dubbed the Petrichor, which could perform cloud seeding, communicating with a ground command station to operate properly. Our team will be responsible mainly for the drone’s communications system, power system, and correct connection of hardware. The end result will be a product that is advantageous over previous and current methods of cloud seeding.
Complete DDR3 SDRAM memory subsystem design with ARM AXI4 and DFI for Xilinx 7 Series FPGA
Kevin Brace, Adithya Visvanathan, BSEE  
DDR3 SDRAM is one of the highest volume memory technology used as of Year 2014. After performing some market research, we have discovered that there is a lack of industry standard centric DDR3 SDRAM interfacing solution for FPGAs. To serve this market, we will develop a complete DDR3 SDRAM controller and PHY solution for the popular Xilinx 7 series FPGA (i.e., Artix-7, Kintex-7, Virtex-7, and Zynq-7000). We anticipate that those performing ASIC prototyping will likely be the primary customer of our design solution.
FPGA Image Processing for Driving
Danh Dang, Duy Phan, Tuan Pham, Thuy Vu, BSEE  
The purpose of this paper is to propose an FPGA-based image processing design for the applications of automotive stereo vision and driving assistance systems. The proposal strictly follows the engineering design flow, including identifying the problem needed to be addressed, investigating pre-existed relevant technologies, deriving project objectives, explaining the state-of-the-art design, acknowledging resources, and managing time.
GPS data sharing in AD-HOC fashion
Sassoun Gostantian, George Mao, Jowey Natividad, Grant Welch, BSEE  
Our team will be working on establishing a mobile RF network, following the basic structure of an ad hoc network. This network will be used to illustrate adaptive networking and communication protocols. For purposes of demonstrating the strength of such networks, GPS data will be used. In the age of high mobility and wireless communication, ad hoc networks provide some of the most flexible and adaptive networking capabilities and are constantly being pushed to the limits under IEEE wireless standards. Implementation of this project is to study and showcase the ad hoc networking techniques on highly accessible microcontrollers. This project would illustrate that relatively affordable devices could be built and be easily distributed amongst a group of people for primarily emergency communication. There may be other groups of people that may use it, such as the military or people oppressed by a strict government. With our current skillset and research of the idea, the project itself is a very plausible endeavor. Additionally, the team will be working with very capable San Jose State University faculty members, Birsen Sirkeci and Robert Morelos­Zaragoza. The team will follow a thirteen week schedule in order to ensure successful results from the project.
Generating Customer Targeted Offers For An Online Retail Site using Hadoop Ecosystem
Pooja Pasupu, MSEE
The project is about analyzing the buying patterns of customers and generating targeted adds/offers for an online clothing store. The offers generated will be based on two factors: Customer preferences: Based on previous Orders/Shipments and amount of time customer spends on viewing each department. Customer Loyalty: Registered customers are offered special perks/discounts on special occasions such as Birthdays/Holidays. Thousands of user records are created to mock actual scenario, the data is processed using Hadoop and its eco system tools, which are MapReduce Flume, HBase, Oozie (scheduling MapReduce jobs) and zookeeper (maintaining HBase servers). Flume agent would be responsible for collecting, cleansing and pre-processing the user data and dumping it into HDFS where data would be aggregated. Periodic MapReduce jobs are executed to process/analyze the data. Output of these jobs is written into 4 different HBase tables each representing a list of customers to whom a specific offer would be sent.
Android SMS Security
Isa Chang, Brijesh Rathod, Kanwalpreet Dhindsa, MSEE  
This project addresses the concerns of SMS based security with the Android platform. Unethical exploitation such as contact hacking and malicious URLs are few of the many techniques hackers use to obtain information illegally. With the recent security breaches at Sony, Target and Anthem Shield, the world of Cybersecurity has obtained the interests of many. The focus of this project is to prevent exploitation through the SMS messaging on the Android platform. The idea is to have a filter which prevents SMS messages with malicious URLs from entering the inbox of the phone. Prior to entering the inbox, the SMS message is quarantined when the URL is extracted from the message and cross-referenced with a database of malicious URLs. Any suspicious texts are then thrown away.
Study of SDN Security Problems
Mengqi Wang, Lening Wang, MSEE  
The Internet has become an important basic facility nowadays. However, the more Internet technologies are used, the more problems can be identified. In order to provide a better quality of service and to enhance the scalability and flexibility of modern networks, Software Defined Networking (SDN) has been proposed. But it also presents many problems. We believe SDN will inevitably face many security challenges such as the vulnerable central controller. This project was aimed at exploring potential network security problems of SDN architecture and enhancing network security performance. In this study, DDoS and illegal access attacks were used to attack an SDN simulation environment. Based on data collection and data analysis, a defense mechanism was proposed and implemented. The strength and weakness in SDN security were identified in the end.
The Design and Implementation of a dedicated circuit for a simple photon transport problem using Monte Carlo simulation
Tushar Kulkarni, Kedar Lahurikar, MSEE  
Monte Carlo is the most accurate but expensive computational method to solve transport problem. With powerful parallel and/or cluster computing system, Monte Carlo calculation can solve simple transport problems near real-time. Due to high price and large size of these systems, there is a need to make Monte Carlo calculation to be possible on hardware. Since FPGA is capable of executing many tasks with high degree of parallelism, solving a Monte Carlo problem on a number of FPGAs is expected to have great performance. In this project, a transport problem with low energy photons incident upon a 3D medium is calculated. Performance between regular computer and one with hardware accelerator implemented on FPGA was compared. The FPGA used is the Altera DE2-115 and the design was efficiently implemented with high level of pipelining and parallelism. The implementation techniques and performance speed-up will be presented and discussed.
Noise and Interference Modeling in WLAN Receiver Front End
Sameera Gunatileka, Sunil Prasad Bindiganavale, MSEE  
This project will simulate multiple wireless receiver architectures such as Super-Heterodyne, Zero-IF, Low-IF, and Hartley, which have become a major problem in designing, analyzing, and optimizing wireless communication systems. The wireless architectures will be analyzed using 802.11 transmitted signal and will draw out their advantages and disadvantages for modern communication applications. Using Simulink/SimRF Library, noise, interference, and distortion will be analyzed in the frontend Wireless Local Area Network (WLAN). Nevertheless, circuit level designing of the first stage WLAN which includes LNA, will be modeled using the Cadence. In-depth analysis of the input and output matching, Noise Figure, gain, and industry level specifications will be validated for the LNA design using 45nm technology.
Demapping for Non-conventional QAM constellations
Quynh Quach, MSEE  
Today’s wireless IEEE 802.11 networks support various conventional QAM (Quadrature Amplitude Modulation) mapping constellations such as QPSK, 16-, 64- and 256-QAM. These constellations correspond to an even-power-of-two number of bits per symbol. However, there is no support of odd-power, or non-conventional, constellations such as 8-, 32- and 128-QAM. This project examines the performance of these non-conventional constellations through their analysis and simulation over an AGWN channel model in combination with log-likelihood ratio demappers and LDPC (Low-Density Parity-Check) codes. Including these unexplored QAM constellations in a wireless network will extend the range of bit rates, compared to conventional even-power QAM constellations alone, resulting in a higher throughput.
Modeling A New Technique Of Phase Detection For Clock And Data Recovery Applications
Deepika Vyas, MSEE  
With the advancement of technology performance of the CDR circuit needs to be improved with increasing data rates. In a CDR circuit the performance is mainly characterized by lower timing jitter and faster locking time. Linear phase detectors inherently have low timing jitter but higher lock time whereas binary phase detectors have lower lock time but higher timing jitter. To achieve these characteristics a new technique of phase detection is developed, which combines the advantages of both linear and binary phase detectors. To test the performance metric three different phase detectors viz. linear, binary and advanced phase detectors were modeled in a CDR loop. Binary phase detector is modified to develop the control logic for advanced phase detector. The simulation result for the advanced phase detector shows effective reduction in lock time compared to linear phase detector and lower jitter compared to binary phase detector.
Design a low power 10-bit successive approximation ADC in 45nm CMOS technology
Saed Mozayani, MSEE  
Over the past few years, there has been a growing need for Successive Approximation Register (SAR) Analog-to-Digital Converters (ADCs) for different low power applications including medical implant devices like the cardiac pacemaker. This device can detect and control the speed and pattern of the heartbeat. The ADC as a critical component in the input block of the device consumes a high amount of power by digitizing the amplified sensed signal. The demand for long battery lifetime in implantable cardiac pacemaker poses the new requirement in design and implementation of low power SAR ADCs. A 10-bit ultra-low power SAR ADC for the first time is designed in 45nm CMOS technology. This unique ADC exhibits a 9.6 Effective Number of Bits (ENOB) with 1kS/s sampling frequency at supply voltage of 1.2V. It consumes total power consumption of 25.67nW and achieves an energy efficiency of 33fJ/conversion.
Dynamic Reconfiguration of Network Based On Security Events
Ram Gandhi Arumugaperumal, Vignesh Ganesh Goutham, Varsha Sundar, MSEE  
This project aims to create a proactive, robust and secured network environment which can counteract ever-evolving cyber threats efficiently over the current methods. To achieve this goal we utilize Software Defined Networking(SDN) technology by adding a security control application on top of SDN controller. Our SDN security application will take instant actions on its own rather than placing all security action responsibility on the user. The main attacks taken into consideration would be DoS, DDoS and other threats following a study of the rare types of attacks. For automatic reconfiguration, various parameters of the network are set, which when exceeds the threshold value, forces the controller to securely reconfigure. The sustenance of the network can be measured by comparing the packet flow before and after the reconfiguration happens. The policy change effected by the controller affects the various layers and the each type of attack warrants different policy change to make the counter-attack more versatile.
Plantar Pressure Measurement System for Running Application
Marilyn Kushnick, MSEE  
Runners often want to know, in real time, how they strike their foot during runs, especially at the end of long runs when fatigue sets in and good form is lost. They also want to know what surface is best to run on to prevent injury and overall running plantar pressure data to aid in buying shoes. In this project, a shoe insert with pressure sensors made from conductive fabric is designed and the collected data is sent to and analyzed by a laptop mimicking a wristwatch application. The raw pressure data is manipulated and displayed to show initial impact point and pressure density.
Adaptive Verification Methodology For Functional Coverage Of An SOC
Mayur Madhusoodan, Prithvin Jaishankar Kumble, MSEE  
The purpose of this project was to develop an automated system that performs functional coverage such that the test cases adapt to successive simulation runs and generate better test constraints for the next cycle. The test bench had a reusable verification environment with a hierarchical structure along with randomized excitation and self -checking mechanism that improved the verification efficiency. This was achieved by constraining and randomizing the signals in the transactor and feeding it to the design under test. The same set of signals was sent to the scoreboard through a mailbox and the golden reference was created. The output obtained from the design was checked with the golden reference in the checker. The functional coverage was increased by loosening the constraints and increasing the number of test cases. Regression testing was also performed to cover all the corner cases.
SDN Switch Design
Rohan Jani, MSEE  
The project demonstrates the design and verification of 5-port SDN Switch Data-Plane, for small-scale commercial and residential enterprise. The project incorporates the flow table block design and data controller with control plane interaction. The open flow pipeline and the data-plane design are based upon open flow specification 1.4.0. The project demonstrates flow|group table functionality based upon openflow protocol along with updating the table with user-defined stimuli. Thus the device presented improves productivity, performance and security by providing Software Defined network control.
On the Design & Implementation of a Low-power MESI protocol
Xiaochen Zhang, MSEE  
This project investigates the design and implementation of parallel computer architecture using techniques to save the leakage current in the multi-core system. The method applied in this project enhances the MESI cache coherence protocol by modifying its state transition to allow cache lines to be turned off with invalidation requests and external signals. The system simulates the function of a two-level cache, in which L1 cache is a direct mapped write through cache and L2 is a two-way associated write back cache. Functional and performance tests on this cache system show that the power consumption of L2 cache is substantially reduced at the cost of slightly larger size of the design and more compulsory cache misses.
Load Balanced Virtual Data Center Network Using SDN Approach
Rahul Cheyanda, Varun Vijayakumar, MSEE  
Data center networks have multiple farms of servers providing a variety of services. The increase in the number of services demands effective compute and network load balancing. Software Defined Networking (SDN), which includes decoupling of data and control plane, can enable an effective optimization of both computing and networking resources, i.e. , network aware load balancing. In this project, an Open-Flow based load balancing algorithm for SDN based data center networks is designed and implemented. The controller effectively chooses the best available server within the pool of servers and computes the least congested path to the selected server. Mininet along with POX controller and the NetworkX Python graph library is used to implement and test the algorithm on the created network. The results obtained are compared with the same network running without any network load balancing algorithm.
An Approach towards Power Verification of RTL Designs
Abhishek Jain, Mugdha Thorat, MSEE  
Power consumption in digital circuits has always been an important aspect of product development. And with the advent of new portable and wearable technologies, power estimation and measurement is becoming a prime factor. Estimating power accurately at early stages of design cycle is extremely critical to achieve the most optimization. This project measured and verified the power values of a design at RTL level. The Device Under Test was “ARM Cortex-M0 IP” obtained from ARM DesignStart Program. With the use of ARM compiler toolchain, various standard test cases were generated. The test cases were in the form of C codes, which simplified the task to a great extent. These test cases were then used to perform Verilog simulations to obtain switching activity. RTL simulation, synthesis, gate level simulations & PERL scripting were some of the tasks being used to calculate the power values.
Design and Verification of MOESI Cache Coherency Protocol
Piyush Kasat, Mandar Raje, MSEE  
This project describes a design and verification technique of MOESI cache coherency protocol used in multiprocessor architecture. In our project we are working on 4 cores each having their private cache and also a shared L2 cache. The goal of this project is measuring the performance of MOESI-SO (Shared Owner) cache coherency protocol and the performance measurement criteria will be the average number of cycles required to serve an instruction. The key feature is the new shared owner state which clearly states the difference between clean data and dirty data. The additional new state is expected to give a performance of 2 cycles per instruction. The results obtained can be compared to those of the conventional version of cache coherency protocols i.e. MOESI.
Load Balancing Utilization in Data Center Networks
Navjeevan Jot Singh Salana, Adarshbir Kaur, MSEE  
The data centers have load balancers to distribute the incoming traffic to various servers present in the server racks. Load balancer is a key element of the data center networks. The topology build is done on network simulator ‘mininet’ and then traffic is passed through the topology. There were various topologies used like mesh, tree and fattree. The project aimed to implement various load balancing techniques. The protocol enabled during the project was OpenFlow. A SDN controller used was POX controller. The results of parameter analysis were obtained correctly after test running different topology-load balancer pairs.
UVM Based Verification IP(VIP) of AMBA AXI protocol
Aparna Rajamani, Vivek Muralidharan, MSEE  
In SoC design, verification consumes more effort than the design itself and has become dominant cost in the design process. With growing complexity in SoC design, verification becomes time consuming and can be source of errors. This project implements an UVM-based Verification IP (VIP) for AMBA AXI protocol. The project aims to build a Verification IP that acts as a plug & play with user configurable module, compatible with all versions of AXI and has the ability to run on multiple simulators. The benefits of UVM based verification includes localization of errors, random stimulus generation, block level testing of design, reusability of verification components and process automation. Details of the implementation will be demonstrated and discussed.
Photodynamic Cancer Therapy employing accelerated Monte Carlo algorithm
T.V.L. Anurag, Balakumaran Srirangaswamy, MSEE  
Monte Carlo is the most accurate but an expensive computational method that can be used in photodynamic cancer therapy. To make the calculation practical, we need to speed up the calculation near real-time. This project implements a Monte Carlo calculation for a simple photodynamic model that represents the transverse of photons through the multi-layer skin on a Xilinx Virtex-5 FPGA. The design consists of a position update block and a direction update block at its core to approximate the position and direction of the photons. Random number generator is used to determine the initial position of the photon and anticipated scattering angle. The next photon position is calculated using logarithm LUT and direction cosines. The direction of the photon is determined using complex Fresnel equations for which sine and cosine LUTs are used. The implementation techniques and results will be presented and discussed.
Adaptive test case selection for maximum functional coverage
Bharath Kala Vasudevan, Abhijith Byrappa, MSEE  
The aim of the project is to maximize functional coverage by using adaptive test case selection for a verification environment. The objective is to identify a minimal subset of test cases from the given set of test cases to yield equivalent coverage. Simulation time taken for subsequent re-runs is expected to reduce as fewer tests will be used. Cover groups have been used to collect data for the decision logic of the algorithm. Adaptive test case selection is performed by using Gradient Descent Algorithm (GDA). GDA identifies the degree of contribution of individual test cases towards the overall coverage. A training data set consisting of repeated iterations of each of the test cases and their corresponding coverage will be given to the algorithm to determine the coefficient of coverage contribution. Based on this knowledge, test cases with a lower coefficient can be eliminated.
Behavioral modeling of a TDC based All Digital PLL
Julian Pinto, Harsha Srirangam, MSEE  
An All-Digital Phase Locked Loop is an alternative approach to a traditional analog Phase Locked Loop for implementation in modern nano-scale CMOS processes. One key advantage of ADPLL is they use digital circuits to achieve the requires filtering in the loop, as compared to bulky analog loop filters that require large capacitors on chip, thus saving a lot of area. Moreover the phase error and other control parameters in the loop are now digital words, produced by digital circuits. This allows for a more attractive digital flow which can be made re-configurable with external assistance through software. This project focuses on a behavioral model of a TDC based digital PLL. Simulink models are created to efficiently model each block mathematically, to achieve time domain behavior. The design elements include TDC as phase error detector, Digital loop filter and a DCO. The ADPLL is characterized in terms of output frequency, resolution, bandwidth, locking speed and jitter.
Design and Implementation of a Universal AHB Verification IP (UAHB VIP)
Ananth Krishnamurthy, Santosh Shetty, MSEE  
Bus protocol is the main communication procedure between components in a system. The AMBA AHB protocol is used to interface most of the components in a SoC circuit. Since the AMBA AHB supports many high performance features such as pipelining, burst transfers, split transactions and also houses an arbiter, verifying the AHB becomes a tedious task. The currently available VIPs for AHB are difficult for users to understand due to several layers inside the test bench and also time consuming due to non-reusability. This project designs and implements a Verification IP (VIP) for AHB core. The VIP is designed such that it is reusable and re-configurable to support all the configurations specified by AHB specification. This includes different address and data bandwidths, transaction schemes, different number of master and slave configurations and various arbitration schemes. Details of the design and implementation will be demonstrated and discussed.
Optimization of Load Balancing in SDN via Switch Migration
Prarabdh Joshi, Anuradha Kannan, Fazil Sarfaraz, Twain Pereira, MSEE  
Software Defined Networks is an increasingly popular network architecture that aims at decoupling the control and data plane unlike traditional routing techniques. For widespread adoption of SDN in the industry, it is crucial to have a federation of controllers for load balancing and redundancy purposes. Also, the static mapping between a switch and a controller becomes a bottleneck. This project is an attempt to develop one such algorithm to achieve load balancing in SDN through possibly seamless migration of switches between controllers based on the alerts raised by a monitoring system which keeps track of the load and other relevant factors of all the provisioned controllers.
Vernier Chain based TDC
Satish Aditya Yanamandra, MSEE  
A Vernier chain based Time to Digital Converter (TDC) used as Phase detector in high performance Digital Phase Locked Loop (DPLL) is designed and implemented in 45nm CMOS technology. Comparisons are made between two different Flip Flop topologies that are simulated in the delay chain. The schematic is capable of achieving pico-second resolution, avoiding limitations in buffer chain based TDC, such as limited resolution to the buffer delay and mismatches. 20-5 bit Encoder block in combinational logic is also developed to convert the thermometer coded TDC output to binary data, which directly represents the time difference between the two signals under consideration.
Enhanced Performance Verification
Naveen Kumar Bangalore Ramaiah, Naresh Khatokar, MSEE  
Verification is most important phase which takes about 60% time of hardware development. So it is highly recommended to reduce the time spent by reuse of verification block. This project presents a new verification approach based on performance metric like frame/second, which works for JPEG encoder. UVM based verification technique is followed in industry for verification and hence it is used in this project. JPEG encoder has multiple stages of encoding which provides opportunity for performance enhancements. These performance issues are found and reported by verification block. This lets the designer to concentrate on a particular block and modify it to meet performance requirements. After resolving these issues, the module is tested using existing verification scripts to find the impact of changes. If the result of changes satisfies the performance needs, one need not go for full system verification again, which saves lot of time.
Implementation of Network Simulator supporting Bluetooth protocol in System Verilog.
Ankit Mehta, Ujjwal Kant, MSEE  
Importance of networking is increasing day by day and so is the need to develop more efficient and fast Network Simulators. The major drawback in the network simulator development is that none of them has ever been built with hardware (RTL) compatibility. Thus, the main idea of this project is to eliminate this drawback. This project involves around the development of Network simulator that is RTL compatible and simulates Bluetooth protocols, which is very unique in terms of its implementation and use. This network simulator is developed in System Verilog that is a RTL compatible language. The uniqueness of this project is in terms of its use as a verification environment to test behavior of baseband controller IP. This method of testing network simulators can speed up their development. This network simulator is not intended to be synthesizable because designs that are designed for synthesis are not good at system level simulation.
Performance Verification of NAND Flash Controller
Sayali Basole, Kriti Ashok, MSEE  
This project is about performance verification of NAND flash controller by creating reusable verification environment. Generic verification environment is built so that any NAND flash controller can be verified by this verification environment. Transactions generated by the environment are sent to the controller, the response received back from controller is checked to verify basic functionality of the controller. To verify the efficiency of memory controller performance verification is done. Verification environment also reports the performance by measuring the latency of read and writes cycle when different sizes of burst are given as an input to the controller. To verify the performance two main parameters are taken into consideration,throughput and latency of a flash controller. By applying constrained random variables and crosschecking the uncovered paths in the controller basic coverage verification is also achieved.
SDN Switch - Packet Parser
Mit Mehta, MSEE  
The project presents a 5 port low cost Software Defined Networking (SDN) switch interface which transfers data from the Media Independent Interface (MII) layer towards the routing tables of our SDN switch in such a way that the processes have an easy access to this data and no errors occur. This project is specially optimized for a low cost SDN switch. Also the design and verification for the project will be provided.
Performance Analysis of virtualized topology using Mininet and Ryu controller
Pinak Karadkar, MSEE  
Virtualization is believed to be the new stepping stone towards more efficient and smarter networking systems. With the advent of technologies such as Software Defined networking (SDN) and Network Functions Virtualization (NFV), several industry leaders have shown their interest in virtualizing their IT infrastructure. In this project, a virtualized topology is developed and implemented on Oracle Virtual box using simulation tools like Mininet. The approach is based on dynamic routing where the controller dynamically finds the best route to transfer a packet from one host to another. A performance analysis has been carried out and compared with more complex topology. In addition to this, we also implement security features such as Firewall and packet filtering.
Controller Evaluation
Vivek Thejasvi Subramanyam, Praveen Kumar Kumsagi, MSEE  
Software defined networking is a concept in the computer networking in which the control plane and the Data plane are decoupled as opposed to the current existing networking models. Our project involves comparing the Open daylight and ONOS SDN controller frameworks on the basis of architecture, interfaces, programmability, reliability/robustness, features, development environment, implementation, etc. In addition we will create a guide illustrating the programming of a number of fundamental SDN use cases such as shortest path L2 or L3 routing, packet interception, etc. Create scripts and/or other helpful tools to aid in installation, configuration, and initialization. Compare the above criteria of these controllers when different number of hosts and switches are connected to them. This should help SDN enthusiasts and students understand and install the controllers easily for their research purposes. Our examples run on Mininet, a network emulator running on a single Linux VM.
Named Data Networking
Aashish Chakrabortty, Karthik Kumar N, Purva Bandekar, Sneha Regmi, MSEE  
Named Data Networking (NDN), a subset of Information Centric Networking (ICN), is a network architecture that revamps network service semantics from “deliver packet to given destination” to “retrieve data with given name.” This project aims at implementing an NDN test-bed in a Software Defined Networking (SDN) context using OpenFlow and POX controller. Key aspects of NDN are implemented in a uniquely SDN manner. For example an "interest" sent from the client to get particular information is intercepted by an OpenFlow enabled switch which forwards this "request" to the SDN controller for processing by our NDN SDN application, after which the real information repository location/URL is sent back to the client. Subsequently, the client accesses the information source to fetch the data. This shift to an SDN approach to implementing NDN as compared to extensive modifications to routers and routing protocols such as OSPF can greatly accelerate the availability of the information centric networking paradigm.
Cloud based Verification of MIPS Microprocessors using UVM
Saurabh Purohit, Udit Jaisalmeria, MSEE  
Our focus in this project is on using Universal Verification Methodology as a Verification Environment to test a group of different MIPS Microprocessors We gather a bunch of designs for MIPS Microprocessors and then check the functionality of the designs to make some interesting analytics. After creating the components we will connect the DUT with environment and test each Microprocessor with the random stimulus generated from our tests. Tests focus on all basic operations performed by the microprocessor. We look to analyze the cloud of designs to find the probabilistic distribution. We will use results to analyze the consistency within the cloud.
Developing and Implementing a Configurable AMBA AXI Core
Moiz Navsariwala, MSEE  
The AMBA protocol is an open standard on-chip interconnect specification for the integration of functional IP blocks in a System-on-Chip (SoC). AMBA protocol allows design re-use by defining a common interface for SoC modules using specifications, which include AHB, APB, AXI and ACE as standard communication protocols. The AMBA AXI protocol is targeted at high-performance system. This project implements a full-scale configurable AXI soft core that can be used in any SoC design. The core is designed and implemented followed the AXI specifications and users can re-configure the core for a wide range of options in SoC integration. The detailed of the design and implementation will be demonstrated and discussed.
Implementation of Wear Leveling Algorithms in NAND Flash Memories
Suraj Kothari, Sneha Iyer, MSEE  
This project developed Static and Dynamic Flash memory wear leveling algorithms. Dynamic wear leveling works on blocks that undergo change and the unused ones. Blocks of data that do not change are not touched by dynamic wear leveling. Static wear leveling works on all of the flash in the system- unused blocks, changed blocks and static blocks. The test data used was from Blktrace block layer IO tracing mechanism which extracts event traces of the i/o traffic from the kernel. NAND Flash memories are used in SSDs, flash drives, memory cards etc. Wear leveling ensures that sectors across the flash memory are erased in an even manner. This helps maximiz the life of NAND Flash memories. Wear leveling is implemented on the Flash translation layer (FTL) which is between the File System and the Hardware Device. Operations on the non-volatile NAND Flash device occur with the help of Progra Erase Cycles.
Optimization of Network
Vipul Ingale, Shaunak Kakade, MSEE  
Our project aims for optimizing the use of underutilized network links to run a network more efficiently and provide better service to network users. In current networks, Ethernet uses multiple trees (e.g VLAN) and shortest path first algorithms. Also, shortest path first bridging (SPB) and TRILL ( Transparent Interconnection of lots of links) are the technologies developed for truly utilizing the links but even they do not take into consideration the bandwidth requested by user and identifying high bandwidth users and placing them accordingly. SDN is capable of doing real optimization. Our aim is to use SDN to enhance the performance obtained by above two technologies and also to obtain better visualization of network and traffic. Also, using existing features of Mininet’s python API, we plan to develop our own network scenarios and achieve optimization in terms of bandwidth.
IOT Device Reliability In a Wireless Network
Priyanka Krishnamurthy, MSEE  
Internet of things[IOT] is a network of uniquely identifiable physical objects accessed through the internet. IOT applications are widespread and it brings important health and safety functionality to a home network. This project studies the impact of entertainment and consumer data on health and safety related IOT devices. Wireless sensor network is a key technology enabling IOT, connects a number of sensors, actuator nodes and devices to the network. A simulation model is generated and data from the model is analyzed. The model is a home network consisting of various mobile and stationary devices with different kind of traffic. The project measures the bandwidth and reliability on access points and the tradeoff between entertainment functions versus the critical functions. Multiple scenarios are evaluated and the results are presented.
Reconfigurable Point Based 3-D Graphics Rendering on an FPGA
Amit Anandrao Ghare, Siddharth Rajagopal, MSEE  
Currently, graphics processing units or GPUs render 3-D objects using polygons or triangles as primitives. As models become more complex, the rendering of individual triangles by the increasingly complex hardware can become inefficient. Where the polygon is mapped to only a few pixels, the overhead in maintaining the connectivity information about the triangles is quite significant. Point based geometries present an interesting and valuable alternative to polygons or triangles. Using points as primitives greatly simplifies hardware requirements and allows hardware flexibility and scalability. Motivated by the limited support for point processing in modern graphics processors, this project presents a graphics rendering pipeline for direct rendering of unprocessed points, tailored specifically for re-configurable systems. The implementation on an FPGA demonstrates the simplicity and effectiveness of the direct point rendering technique and highlights the feasibility of the re configurable platform. Details of the implementation techniques and performance results will be demonstrated and discussed.
Implementation of NFC Protocol
Dikita Chauhan, Puja Vaze, MSEE  
Near field communications (NFC) has its roots at RFID. NFC has a shorter communication range of 2-3 cm and is more secure than the other RFID subsets. This project involves building a NFC IP core by implementing the ISO/IEC 14443 protocol (layer 3 and 4). A standalone NFC IP would be more power and area efficient as compared to an IP which has other wireless technologies such as Bluetooth and Wi-Fi bundled together with NFC. The project includes writing a synthesizable RTL Verilog code, verifying the individual blocks using System Verilog verification environment and porting the design on to an FPGA. The design would include blocks for encoding/decoding frames, tags and all the related protocol handling. This would make a standalone NFC IP available which could be easily included into an embedded SoC.
Performance Verification of Memory Controller using System Verilog
Chinmay Shekhar Tambat, Tejas Suresh Shetty, MSEE  
This project performed System Verilog performance verification of an Altera Quartus DDR2 SDRAM Memory Controller. Performance parameters considered are Read Latency, Write Latency, etc. Performance verification is essential in determining system's memory controller effectiveness and data handling capability of the memory. The simulations were observed using ModelSim.
Design and Implementation of SIFT on FPGA for Autonomous Vehicle Vision Applications
Viswateja Nemani, Arjun Vijaymohan Kandukuri, MSEE  
The SIFT (Scale Invariant Feature Transform) algorithm is widely used in various image detection and image matching applications. This computer vision algorithm does a key point extraction and detection to process an image and extract local feature vectors that are immune to any scaling, rotation or translation of the image. This paper discusses hardware implementation of the SIFT algorithm on an FPGA. We describe methods to accelerated hardware solution on FPGA to process images using SIFT. We describe hardware modules for the Down-samplers, Gaussian-filters and for computation of difference of Gaussians using Verilog to aid in expediting the process of this algorithm. Design Process involved developing a MATLAB reference module, along with python scripts. The RTL is developed in Verilog, tool used is Xilinx ISE-14.4 and targeted device is Xilinx FPGA-Spartan6. The Algorithm requires approximately 100k-LUTs and 1Mb on chip memory. Future work involves optimizing resources, and adding object-tracking features.
Implementation of Software Defined Networking in a Data Center Environment
Gokul Anudeep Pokuri, Jayashree Naidu Kotte, MSEE  
Software Defined Networking (SDN) is a trending technology in IT industry. There is enormous pressure on conventional routers to perform better with huge traffic and heavy bandwidth requirement. To decrease load and increase efficiency of routing, SDN provides a good optimized solution. With the implementation of SDN in a data center network, providing centralized control could eliminate major issues of routing. In this project, we develop codes for router functionality. Implementation of routing in data center environment with various topologies is done. The tools being used are Mininet, Vswitch, Floodlight controller and VMware workstation. Python language is used for scripting. In Mininet we create customized topologies using python scripts, and implement them using Openflow controller to determine SDN's efficiency. After designing and implementing the network, DCN functions under centralized control that makes it easy to implement rules as required, overall bandwidth would be increased and latency would be decreased.
Design and basic functional verification of re-usable IP of L2CAP layer of Bluetooth v4.1
Arafat Ansari, Mandar Saundattikar, MSEE  
This project presents an IP (Intellectual Property) Design approach of L2CAP layer from the protocol stack of Bluetooth v4.1 using Verilog as Hardware Description Language for implementation and functional verification purpose. The inspiration behind choosing implementation of L2CAP layer in Digital domain lies in the fact that Bluetooth being an active element of today’s communication world and consequently dominating the Internet of Things network by large proportion. The functionality of the design is extensively verified in order to meet the Bluetooth v4.1 specifications as mentioned in the core manual by Bluetooth SIG group. The project ensures the availability of a re-usable IP of L2CAP layer which can be directly integrated in Bluetooth oriented networking applications for simulation purpose.
Performance Analysis of Virtualized Network Topology and Functions Using Mininet
Bharadwaj Ananthula, Surya Abhijith Kumar Devaraju, MSEE  
The project primarily presents the emulation of virtualized network topologies and to enable different network functions like Routing and Firewall using tools like Mininet, Virtual Machines, OpenFlow and Wireshark. Virtualization technologies like NFV and SDN are considered in this project. Focus is also laid on the other virtualization scenarios like creation of Virtual LANs and communication between the hosts using RYU Controller. Virtualized networks become important to meet the challenge of deployment and installation of new hardware each time a new service is required. They are also more adoptive, responsive and consume less power compared to traditional network system. Finally, performance evaluation of these network functionalities will be carried out based on various parameters like bandwidth, latency, jitter, TCP window size, time and other factors.
Consistent Model Architecture for Scalable Infrastructure Systems for Big Data Processing
Navyatha Marreddy, Prita Nigam, MSEE  
Nowadays, data is being created in such huge amounts and in varied forms that it cannot be handled by conventional tools and technologies, popularly known as Big Data. It requires advanced methods to handle it. We have chosen this challenge of Big Data and wished to develop a consistent model that processes the incoming tasks in minimal time and in an efficient manner considering two problem statements for our project:
• Portfolio pricing
• Counting words in dictionary
The exclusiveness of the idea is not to submit the task data with the task. We keep all data separately in a Data Grid domain. Our main component in this task, Job Dispatcher (JD), divides the input job in an efficient manner and distributes them to Computing Grid nodes, which are responsible for processing the tasks, and sending the result status back to JD and putting the results in Data Grid. The Job Dispatcher aggregates these results.
Optical Flow/Motion Detection
Vishal Prajapati, MSEE  
This project involves a system design that can detect and display optical flow/ motion of moving objects in the background of any real time video captured. The project is being developed on the SoC board- Xilinx Zynq ZC702 and for the real time video input, I am using FPGA mezzanine card FMC-IMAGEON. For the motion detection of any object between two frames, Corner Harris and Sum of Absolute Difference algorithms are being used. Arrows are shown to display the optical flow of any object moving in subsequent frames. I am currently working on a full HD video of resolution 1980x1080 with a frame rate of 60fps. Operating frequency is 150Mhz. I am working on improving the algorithms to get strong motion vectors and noiseless performance as the results.
Monitoring and Filtering application in SDN
Anil Kumar Reddy Kona, Noorinbano Shaikh, Sneha Viswalingam, Anudeep Reddy Ramashayam, MSEE  
Today’s networks are evolving to be more application aware that changes user experience for the better and reduces operational costs . Traditional networks were designed to forward packets from source to destination using the shortest route possible. This project shows how the Software-defined network (SDN) architecture allows service providers to build networks with increased application awareness, which can be built into the network by developing SDN controller applications that filters the application-level characteristics and use that intelligence to provision flow into the network switches. This defines a monitoring application which is a software program that sits on the controller and oversees the traffic in a software defined network as a component of network management. The controller inspects packet header and payload, determines the type of packet and installs a policy on the switch to forward packets along the desired route as specified.
SSD NAND Flash memory reliability verification using Wear Leveling
Umang Shah, Mihir Shetye, MSEE  
Wear leveling techniques (Static and Dynamic) were developed to improve reliability of NAND Flash memory cells. A combination of the two existing techniques were used to develop an algorithm that uses the best of both worlds and helps tackle the long prevalent issue of NAND Flash wear out. IEEE papers such as Rejuvenatory, High Performance Wear Leveling Algorithm for Flash memory system and Reliably erasing data from Flash based SSDs were referred to develop this algorithm which was then rigorously tested and tweaked. Equalizing program-erase cycles among NAND Flash cells thereby improving overall reliability was achieved. Data gathered from building and erasing a Linux kernel using blktrace was used to test the developed algorithm. Testing parameters for data migration were studied and an optimum range for them was concluded. A reliability ratio was also calculated to judge the algorithm's performance.
Behavior of Security attacks in Software Define Network
Akhil Goel, Amit Chaudhary, Maulika Vashishtha, Pranusha Boinpally, MSEE  
Managing network and handling the network security is a big challenge. The scalability of the network is not flexible once the routing architecture is defined. To simplify the mobility and control the traffic of the data and also to reduce the cost of the traditional network, Software Define Network (SDN) is a promising architecture. SDN handles the automation of the network traffic flow and assist in easy implementation of complex applications in the network. But security is still fragile concept in SDN and more research is required to build a robust network. This project work shall contain the information of the security behavior of different topologies in the network. This research emphasizes the observation of DDoS attacks using various controllers like, POX, Flood light, etc. and also prevention of the same. The study shall be done under the guidance of our advisor.
Performance Evaluation of Matrix Multiplication on two RTL (Verilog) Designs of Cache Controllers, designed respectively based on Intel Nehalem and AMD Opteron (Shanghai) Cache Architectures
Sai Dheeraj Polagani, MSEE  
Chip-Multicore technology has now become a vital force driving the performance improvements in today’s microprocessors. As the processing units gets faster, the Memory sub-system has been found out to be a bottle-neck to utilize the complete performance boost provided by the microprocessor cores. In this scenario, the introduction of the on-chip cache memory into the memory sub-system has provided a way to boost up the memory sub-system performance. In a multi-core scenario, cache architecture becomes crucial as the cores tries to share the available memory on the chip. This project deals with performance evaluation of two such cache architectures. The project tries to come up with two RTL level (in Verilog HDL) designs of Cache Controllers, based on Intel Nehalem and AMD Opteron (Shanghai) Cache architectures. The paper picks up the cache architecture in a quad-core environment; the micro-processors being targeted for high performance Desktops. Matrix Multiplication has been chosen to be a benchmark application for evaluating the two cache architectures.
Subpixel Estimation for Real Time Stereo Vision System
Pramoda Achalla, MSEE  
Subpixel estimation for real time stereo vision system is an important problem when the input video resolution is not high enough. The objective of this design is to implement the subpixel estimation in an optimized manner without using classical interpolation method. To avoid expensive cost of interpolation, we implemented block matching algorithm along with Taylor series approximation to get motion vectors. We implemented different methods of block matching algorithm along with Taylor series and compared the resulting motion vectors of them with those block matching methods along with interpolation. According to Matlab simulations, the computational time to calculate motion vectors by this method is 42.5 times faster than the interpolation method.
Interfacing BIST with NAND Flash Memory using NAND Controller
Varun Patel, MSEE  
This projects targets to design BIST model for covering faults with an optimized algorithm, which interfaced with memory using MLC NAND controller. Considering the NAND memory behavior for different aspects of erase and program cycle, NAND flash array structure we implemented an optimized algorithm for program, verify, read and erase. The NAND simulation model used in this project is sourced from Micron Technologies, is 16GB MLC series memory module, which is used as reference memory for implementing BIST model. This model consists of test pattern generator to focus tests on desired faults and coverage, a test controller to control and generate test content data, and a response analyzer logic that decide memory being fault-less or corrupt. By implementing boundary parameters such as execution time and reliable testing through BIST, this project eyes to optimize BIST design interface with memory using NAND flash controller.
Model Based Object Detection Using Mono Vision Camera on Raspberry PI B+ Embedded System with Broadcomm GPU
Vivek Kumar Anchalia, MSEE  
Object detection has been one of the most extensively researched technologies with leveled difficulties interrelated to computer vision. For efficient object detection, features of all objects present on a given image are detected for later processing. The objective of our project was real time application implementation, recognizing the features of the presented model, based on the algorithm, tracking back and identifying from the database of acute visual features. A computer system which can recognize a subject was developed. It differentiates any individual object by weighted sum of Eigen object features. We have implemented this system on Raspberry PI hardware, with a monovision CMOS Image Sensor Pi camera, which has a Broadcom SoC , GPU to accelerate frame rate . Current frame rate achieved was 18 f/s with 640x480 resolution. A similar feature for detecting car models including face detection feature is on process. Future work will be to identify, track and predict the movements of on road objects.
UVM Verification of DMA Controller
Neal Israni, Akshay Tamboli, MSEE  
This paper demonstrates a verification plan to verify DMA controller core using Universal Verification Methodology (UVM). Power of the DMA controller can be verified by using the verification IP described in this paper. This paper incorporated a new approach to verify power, and Universal Verification Methodology was used to verify power of DMA controller. In this project, power verification was done by applying test cases from testbench to the design under test. The testbench was created by using Universal Verification Methodology (UVM) standard libraries that were available in System Verilog. The motivation for this project was that in semiconductor industry, power verification of any device is not done by using Universal Verification Methodology.The significance of this project was that in industry, low power devices are in demand. One can have a high performance device but to have a device that can consume less power is more important.
Usage of Evolutionary Algorithm (Genetic Algorithm) to maximize Functional Test Coverage in ASICs.
Vikram Vasudev Kamath, MSEE  
The functional test coverage is increased in ASICs by improvising the verification techniques. The standard verification methodologies such as Universal Verification Methodology and Open Verification Methodology consume huge amount of time for testing the functional correctness of the design. So considering the disadvantage, there was a need in the rise of some improvised verification technique which is less time consuming than the conventional methodologies. This doesn’t mean any compromise with respect to functional coverage of the design. The proposed methodology is designed to give the maximum test coverage and high functional correctness in ASICs. This methodology is a new algorithm which is called Evolutionary Algorithm. This algorithm extracts most of the concepts from the Genetic Algorithm. It is almost the same as Genetic Algorithm.
Simulation of Peer to Peer Network Using Chord Protocol in NS2
Srinidhi Hari, MSEE  
Chord protocol is gaining popularity and is being widely used in peer to peer networks for file identifications in nodes. The primary problem that exists in the present day peer to peer is identifying the node that stores a particular file, chord protocol efficiently solves this problem mainly because of its circular architecture and routing architecture. The chord protocol just like any other peer to peer protocol consists of a decentralized network. This protocol addresses the key factors of peer to peer networks such as scalability, effectively identifying the node containing the key and leaving of a node holding the key of an item. The protocol is implemented using distributed hashing table on a simple topology using a network simulator called NS2. The main performance metrics: the time taken in key identification, in a complex network; the scalability limits of chord are measured.
Simulation of Independent Peer-to-Peer Network
Jeeva Munusamy, MSEE  
It has been estimated that Peer-to-Peer file sharing accounts to over half of the traffic that flows across the Internet. This serves as the motivation to simulate an independent Peer-To-Peer network using the NS3 network simulation tool. The objective of the project is to setup an independent P2P network topology that can function without being connected to the Internet. P2P file sharing is performed among the peers and the file download time is noted. Once this simulation is successful, the scalability of the network is tested by attaching additional nodes to the initial topology. Then the download speed of the simulated independent network before and after the addition of new nodes are compared. The desired result is that, due to the effect of scaling of nodes, there is a reduction in the time taken for file sharing.
Passive UHF RFID reader signal analysis using a software-defined radio.
Navpreet Singh, Nived Bedachuvally Nataraja, MSEE  
This project deals with signal analysis of reader-to-tag links of passive UHF RFID systems by using a software-defined radio. Two outcomes of this work are: (1) Spectral analysis of frequency hopping patterns; and (2) demodulation of PIE (Pulse Interval Encoding) signals sent by the reader. To accomplish both of these tasks, the reader signals are captured via the antenna of a USRP2 (Universal Software Radio Platform version 2) radio in a data file using a Matlab Simulink model. Results are presented using subsequent frequency-domain and time-domain analyses that are performed using Matlab scripts.
Scalability concerns in Software Defined Networking
Prachi Dalvi, Shraddha Bhosale, Padmanabha Praveen Chavvakula, MSEE  
Software Defined Networking (SDN) is emerging network control architecture. SDN decouples the network control plane and data plane and provides standardized interfaces for the control of the data plane. SDN allows logically centralized control of network. This feature has led to questions about the scalability of an SDN control plane. Simultaneously, many modern applications, such as those running in large datacenters, have come up with innovative ways to achieve scalability. We wish to investigate one class of such techniques, object database clusters, to SDN. Our aim is to compare the scalability issues involved in traditional OSPF network with that of an SDN utilizing modern object database technology to store network control plane information. We will investigate properties of NoSQL databases most appropriate for network control plane data. In particular looking at consistency, availability, properties of various NoSQL databases and select and demonstrate the most appropriate for SDN control plane.
High Performance DDR4 Memory Controller for Adaptive Page Management Policy
Krutika Gulvady, Mahesh Glv, MSEE  
This project improves the performance of DDR memory controllers by targeting row access latencies, which are more prominent as compared to column access latencies. The DDR4 DRAM is the latest industry standard of memory modules for SoCs. DRAM controllers struggle majorly with data access latency issues. This project inspects the performance improvements that can be achieved by adaptive page management policies. The project demonstrates a unique dynamic logic block, which decides on whether Open Page or Close Page policy can be used for the next instruction based on pre-fetched instructions. The latency drops significantly as a result of implementing this technique. The performance improves with least increment in logic area on chip.
Developing a firewall for SDN
Krishna Mohan Lankala, Kartik Moolani, MSEE  
Task: Developing a firewall for SDN
Objective: Policy rules must not be overlayed, decayed, shadowed and conflict.
• Defining a firewall that spanned to application, control and data layers of SDN.
• A policy manager will be defined that splits policy rules and evaluates the rule conflicts in the hierarchy of network layers.
• Network transactions will be evaluated by the firewall in the order of network layer hierarchy. This helps to avoid the conflicts raised between rules. Also helps to minimize the number of rules during network transaction valuation, but number of valuations will increase, which is inevitable.
• Policy manager handles the intra, inter layer dependency.
A simulation model of the SDN will be devised by using SDNsim API. Further a SDN packet generator will be devised that is compatible to SDNsim. The cross layered firewall and policy manager will be implemented and tested on simulation model of the SDN.
Development of Reconfigurable and Reusable Verification IP for AMBA ACE Protocol
Sameeksha, Sivaprasanth Iluppur Thiyagarajan, MSEE  
Verification of AMBA 4 ACE is a huge challenge for verification engineers considering the protocol complexity and the abstract cache state transition. The currently available verification IPs are hard for customers to understand due to several layers inside the Testbench and also time consuming due to non-reusability. This project developed a reconfigurable, reusable and user friendly verification IP for verifying the AMBA 4 ACE interconnect designs. The VIP supports constrained random stimulus generation, an interconnect monitor to check the transmission of data and a coverage model to verify the coherency of the design. With the help of well-defined assertions, the VIP is able to test the abstract cache state transition of the ACE designs. Details of the implementation will be demonstrated and discussed.
Implementation of a DDR3 SDRAM Memory Subsystem on a Xilinx 7-Series FPGA with ARM AXI4 and DFI
Michael Wilk, MSEE  
DDR3 SDRAM is the one of the most ubiquitous memory technology utilized in high-end embedded applications, tablets, laptop computers, desktop computers, servers, etc. It is also widely used in conjunction with FPGA hardware-based applications. While there have been many FPGA vendor supplied DDR3 SDRAM controller and PHY solutions, most solutions rely on a proprietary interface between the DRAM controller and PHY. We have created an industry standard-based DDR3 SDRAM PHY for Xilinx 7 series FPGA utilizing DFI (DDR PHY Interface). DFI is a standardized interface widely used in ASIC design to connect DDRx SDRAM controller to DDR interface PHY. To verify the functionality of our DFI PHY, we also developed a DDR3 SDRAM controller with ARM AMBA 4 AXI4 protocol and a traffic generation verification vehicle. We have used Xilinx AC701 evaluation board to verify our design. We achieved 667 Mbps operation with Xilinx Artix-7 XC7A200T-2 device.
FPGA based Stereo Vision System Design
Chintan Varia, Waleed Syed, MSEE  
Stereo vision is one of the most important subjects in automation field for developing a reliable distance calculation hardware system, which could be in driver less cars. The hardware calculates the depth of the object in the image by comparing frames received by two cameras at the same instant but displaced on the horizontal plane. Correspondence computation would involve finding the position of object in both images and relative positioning of object in the frames, along with the some other parameters such as distance between camera and focal length was used to calculate the distance of the image using triangulation theory. The design flow involved prototyping of modules on MATLAB. Later the code was developed in Verilog for hardware implementation. Xilinx Nexys4 platform had been used in the project. We had got the processing rate of 30 fps with the resolution of at least 164 x 164 pixels size frames.
A FPGA based Real Time Stereo Vision System with a Improved SGM Path Cost Propagation Method
Chia-Pin Tseng, Boyang Wang, MSEE  
Stereo Vision is used in robotic vision and autonomous vehicle navigation. The Semi-Global Matching algorithm is one of the most widely used stereo vision algorithm. The objective of this project was to implement the SGM algorithm to enable real-time performance on input video on a low-cost FPGA. We used Xilinx Spartan-6 FPGA and VMOD-CAM to achieve the real-time SGM based stereo vision system. This implementation utilized 54,576 slices registers, 2,288 LUTs, and the maximum pixel clock frequency reached to 71 MHz. The resulting performance is equivalent to processing HD stereo video sequence at the rate of 40 frames per second, generating 32 pixel range disparity maps. We also introduced a branch cost propagation method instead of straight paths cost propagation in SGM algorithm to make aggregation even close to global matching. The branch cost propagation method reduced 10% average error under absolute difference (AD) metrics.
Fast Matrix Multiplication IP for Face Recognition Applications on Xilinx SOC FPGA (Zybo Board)
Sai Agnihotri, MSEE  
Face recognition has become extremely critical in many applications. The code profiling study shows that matrix multiplication is the most computation-intensive function of the algorithm and accounts for 80% of the total time. Therefore, the objective of this project was to develop a FPGA based fast matrix multiplication unit which can be used as a hardware accelerator in face recognition systems. The matrices of 32-bit-fixed point unsigned integers were subdivided to form the blocks, which were multiplied in parallel to utilize the resources available on FPGA. The design was modeled in Verilog-HDL and simulated using Xinlix Vivado 2014.3 tool. The synthesis was done by targeting the Atrix-7 FPGA of Zybo Zynq-7000 development board. For realization of this unit 4005 LUTs, 64 DSP48 slices and 128KB BRAM was required. The design was successfully tested on 100Mhz frequency. For real-time face recognition, the designed unit will take 4.5ms for one QVGA frame.
FPGA Based Real Time Optical Flow Computing
Abhishek Khule, Minjal Patel, MSEE  
One of the key tasks in driverless car is computing optical flow of the objects around the car in real time. The goal of this project is to implement FPGA based real time motion detection. For higher performance, this project pipelined Harris corner detection algorithm followed by SAD (Sum of Absolute Differences) algorithm against the traditional approach of calculating SAD values for all pixels. The algorithms were modeled using C/C++ and verified under Xilinx Vivado environment.To implement it as a hardware accelerator, bit streams were generated using Xilinx SDSoC tool. Then the system was implemented on Xilinx Zynq zc702 with a FMC imageon card on it. Hardware runs at frequency of 150 MHz and utilizes 30K LUTs.The resulting system can run for video stream with HD resolution of 1980x1080 at 60fps. Future scope includes benchmarking the algorithm against traditional algorithms implemented on FPGA and GPU.
Vehicle tracking IP using Xilinx SOC FPGA(Zybo Board)
Aman Kumar, Parag Rao, MSEE  
Feature extraction and motion estimation play a very important role in autonomous vehicle navigation. The objective of this project is to track the direction of motion of a host vehicle using FPGA system. Feature points of the input frame were calculated using the “Corner-Harris” algorithm. Employment of SAD (Sum of Absolute Difference) on the current frame against a previous frame on these extracted features points provides an accurate direction of motion of the host vehicle. Algorithm was implemented on Xilinx FPGA Zynq 7000(Z-7010) SOC board using Vivado HLS Video Libraries. A high quality video input (1920x1080) of a moving vehicle, with a frame rate of 30fs, was used for testing the application. There were 5000 logic elements, 70 DSP48 slices and 128KB BRAM required for realization of this unit. The design was successfully tested on 100Mhz frequency. Future work includes increasing the computational speed of the algorithm.
Real Time Optical Flow Computation on FPGA
Vrishbhan Singh Sisodia, Virendra Kate, MSEE  
One of the important aspects of the driverless car is analyzing the changes in the surroundings for a safe and a comfortable ride. Our project aims at designing an FPGA based system that computers optical flow of surrounding objects and mapping the motion vectors to show the movement in the two successive video frames in real time. The design is based on Harris corner detection and performing SAD (Sum of Absolute Difference) based block-matching around the corner points. The algorithm was implemented in C++ using OpenCV for testing, and in Verilog HDL for hardware implementation. The synthesized design was ported on Xilinx Zynq ZC702 SOC board running at 150MHz and utilizing approximately 25k LUTs to process real time HD (1920x1080) video stream at 30fps. We used FMC-IMAGEON mezzanine card for providing HD video input. The future work may include calculation to detect potential hazards and adapt accordingly to avert them.
Real Time Optical Flow Computation on Xilinx SOC FPGA
Akshat Agrawal, Aayush Modani, MSEE  
For Driverless cars, one of the most important tasks is to detect the direction of the relative motion of objects around it. Therefore, the objective of our project was to design a system which can detect motion and display the optical flow in real time. Implementation of the project was done on Xilinx ZynqZC702 SoC board and for the video input, FMC-IMAGEON card was used. ‘Corner-Harris’ and ‘Sum of Absolute Difference’ methods were used to detect motion between two frames. The optical flow had been displayed using arrows to show the movement of the object. The project was implemented in C++ for testing the algorithms, and in Verilog for hardware implementation. The processing was done on HD quality Video i.e. 1920x1080 frame size, with frame rate of 30 fps. Around 27k CLBs were used with fmax of 150 MHz. Future work may include improvement in the performance of the algorithm.
Designing Feature Extraction Algorithm on Altera FPGA
Dhanashree Lonkar, Kartik Parate, MSEE  
The objective of this project is to implement feature extraction algorithm for computer vision on Altera FPGA to enable real-time performance on input video. The algorithm we have implemented does not require any floating-point operations. The project detects corner point in the image using threshold values. This detection is purely based on selecting the value of threshold. Real-time performance can be achieved by implementing the algorithm on FPGA. The algorithm was modeled in Verilog and synthesized on a number of Altera FPGA family devices. For real-time demonstration, we implemented the algorithm on Altera DE-1 FPGA board containing Altera Cyclone II FPGA. The implemented algorithm requires 16.8K Logic Elements and 8 Mb of off-chip memory with the maximum operating frequency of 50 MHz. The current results demonstrates that our system can work real-time for HD (or VGA or QVGA) video with 30 frames per second. Future work may include adding our circuit as a hardware accelerator to SOC FPGA, such as Altera Cyclone V.
FPGA Based Design of Disparity Map Calculation for Stereo Vision System
Kalpesh Dave, Suchit Sanghavi, MSEE  
The project presents a hardware for real time disparity map calculation for stereo vision system design which was implemented on a single FPGA. The proposed hardware architecture uses stereo vision algorithm based on Sum of Absolute Difference (SAD) algorithm to compute the disparity map of stereo images. The SAD algorithm was first tested in MATLAB for standard stereo video sequences. It then was modeled in Verilog, synthesized and tested on various families of Altera FPGAs, under Altera Quartus II 13.0 tool environment. The design summary shows our design requires 43716 LEs and works at maximum frequency of 90 MHz on Altera Cyclone II. For 640 x 480 pixels VGA image, the proposed system can process up to 23 f/s with maximum disparity of 64 pixels. The proposed system was tested in indoor environment using Altera DE2 FPGA board. Future work is to develop obstacle detection system in real time using V-Disparity map and Hough Transform.
FPGA Based Stereo Image Rectification
Anusha Chennupati, Ankita Chaturvedula, MSEE  
Image rectification of stereo images is the process to eliminate the geometric errors that occur due to the disorientation of the stereo camera. The objective of this project is to design an FPGA-based stereo image rectification system that efficiently implements stereo image feature extraction and rectification. Points of interest are detected and extracted from a stereo pair of images using the MSER (Maximally Stable Extremal Regions) Algorithm and the images are rectified by applying an Affine transform for rectification. The system is implemented on Altera DE1 FPGA using Altera Quartus II EDA tool. The algorithm was first modeled in Matlab for verification, and then in Verilog HDL for hardware implementation. The proposed system requires approximately 18,700 LEs and is 20% faster than the software implementation of the same, and can process a standard video (640 x 480 pixels) at 100 MHz.
Parameterizable FPGA Design of Deep Neural Network
Jigar Bipin Desai, Abhishekh Pai, MSEE  
Deep neural networks have recently been achieving state-of-the-art performance on a variety of pattern-recognition tasks, most notably visual classification problem. The objective of this project is to design, implement a parameterized two-layer neural network using pipelining technique using FPGA. We designed a parameterizable pipelined two-layered feed forward neural network in verilog which has proved capable to approximate any arbitrary function, given that they have sufficient number of nodes in hidden network. We also designed User Interface called DNN Builder to provide parameterized inputs to the design. The design was simulated and synthesized using Quartus-II 13.0 tool environment. The design utilized 3295 to 8697 LEs depending upon the number of nodes selected by user and works at maximum frequency of 100MHz on Altera Cyclone II. The processed system was tested in indoor environment using Altera DE-1 FPGA board. The results are calibrated and observed on DNN Builder for various Weights and Bias weight of individual neurons in a network. The future work would aim at reducing the cost by using a single network to detect objects of different classes and thus expand to a larger number of classes.
FPGA-Based Sparse Matrix Multiplier
Suchet Gundugollu, Ramya Krishna Nerusu, MSEE  
Sparse Matrix operations are required in a number of applications including Audio signal processing and compression. A sparse matrix, contains zero value elements at most of its positions. The ratio of the number of zero elements to the total number of elements is called the sparsity. This paper focuses on multiplying sparse matrices using FPGA. This needs to be relatively easy to scale, so that the size of the matrix involved can only be limited by the amount on on-chip memory present to create the LEs(Logic Elements). Each Row/Column data is stored in two FIFOs. One stored the incremental position, and the other stored the value present. These values are then sent to the pre-computation module. The pre-computation module processes cases where zero values are involved, so that the MAC module bears lesser overhead. As of now, we are working with 16X16 Matrices, with a maximum FIFO size of 16 values.
Design of High-Speed Memory Controller using AMBA-APB Protocol
Shraddha Punjabi, MSEE  
In today’s world of multi-core processors, the system needs equivalently fast memory speed to synchronize with. Unfortunately, in some systems the speed of data transfer to and from the memory is slower than processor’s speed. A fast memory controller synchronizes the speed of processor with the speed of memory. Therefore, the objective of this project was to design a high speed memory controller using APB bus protocol. The internal multiplier of the processor multiplied to the Front Side Bus (FSB) speed determined the speed of the memory. The internal multiplier of a processor is always a fixed value, so speed of the memory controller was increased by increasing FSB speed. The internal multiplier of the processor was 16 bit in this project; the speed of FSB was set to 200 MHz, 300 Mhz, and 450 MHz and the corresponding memory speed achieved was 3.2 Ghz, 4.8 Ghz, and 6.4 Ghz.